RIA: The Design of High-Performance Asynchronous Controllers

Nowick This research concerns the development of algorithms and software tools for the design of asynchronous circuits. Previous work in the area has produced a 'locally-clocked' asynchronous design style, which produces high performance implementations that are hazard-free at the gate level. Three extensions to this design style are being investigated. The first is to explore an alternative unclocked asynchronous controller design method, which only requires a single feedback cycle to implement a state change. This work includes implementation of generalized burst mode specifications to the unclocked state machines. Second is the development of extensions to hazard-free logic minimization. The extensions include: a heuristic two-level minimization algorithm; an exact product-of-sums solution; time-optimized multi-level logic synthesis; testing oriented two-level minimization; and hazard-decreasing, multi-level transforms. Third is an exploration of systematic ways to test asynchronous designs.