SHF: Small: An Asynchronous Network-on-Chip Methodology for Cost-Effective and Fault-Tolerant Heterogeneous SoC Architectures

One of the grand challenges of the next decade is to provide cost-effective and systematic approaches to build large-scale computing systems to meet the country's future technological needs. Such systems will involve 100s or 1000s of processors, or more, on a single computer chip, which perform massively parallel computation tasks, and can be housed in either large data centers or even in desktop or hand-held consumer products. Such parallel computing is the key to supporting the continued growth of social networks (texting, Facebook) and rapid Web queries, as well as solving massive scientific computation problems, such as for weather, oceanography, air traffic control, military, and security. However, there are currently severe cost overheads in designing such systems: huge energy usage, thermal overheating, poor delivered performance, and complexity in assembling such complex and varied components into a single chip. Many of these bottlenecks have been exacerbated by the traditional use of a fixed-rate clock, which centrally controls all components on a chip. The goal of this research is to explore and significantly advance one highly promising alternative solution: to build ?plug-and-play? easy-to-assemble computer systems without any global clock, but instead through asynchronous (i.e. clock-less) assembly. Such a solution promises much lower energy consumption, and ease of assembly, of such systems. The project will also train students in asynchronous circuit design and the general area of information and computing technologies.

The particular focus of this research is to develop structured digital interconnection networks for a chip, called 'networks-on-chip', which form the 'backbone' of recent commercial parallel computer systems. While initial solutions with asynchronous design have been promising, they have lacked fundamental features needed to make them viable for industry. In this proposal, several key features are developed for asynchronous networks-on-chip: error detection and correction, performance enhancement, and automated design flow. The approach will also be applied to a realistic cell phone application, to demonstrate the ease-of-design and cost benefits. Taken together, this new approach promises a significant advance forward in providing the capability to assemble complex parallel computer systems needed in the future.