Testability and Sequential Optimization of Asynchronous State Machines

This research is part of a long term effort to migrate techniques for synchronous design to asynchronous design. The two focus areas are sequential optimization and synthesis for testability. In the former, problem formulations of input, output and input/output encoding are being investigated. In each case, the problems of optimality, race-free encoding, and hazard free logic are being solved simultaneously. In the latter, synthesis of fully testable asynchronous state machines using partial or no scan is being pursued. Design tools, incorporating the algorithms for optimization and synthesis for test, are being developed.