Stochastic VLSI synapses for robust classification in neuromorphic electronic circuits

Neuromorphic Very Large Scale Integration (VLSI) hardware offers a low-power and compact electronicsubstrate for implementing artificial neural networks with distributed plastic synapses. However, thistechnology is typically characterized by limited resolution and high intrinsic variability. Therefore,neuromorphic synapse circuits are inhomogeneous and imprecise and thus the mapping of standardlearning models onto this hardware is practically unfeasible. For this reason, this problem of variability isconsidered as an unavoidable “bug” that needs to be minimized. Typical methods used for coping withdevice mismatch and limited resolution resort to using very large devices and circuits or to off-loadingthe complexity of the synapse model to external digital resources. However, these brute-force solutionsintroduce communication bottlenecks and compromise compactness and power efficiency.In this project I propose to implement a hardware neural network that exploits intrinsic variabilitythrough stochastic learning for implementing efficient and robust VLSI neural processing systems and forexploring brain-inspired computational principles. The network consists in an ensemble of neurons withplastic synapses and stochastic learning that receive input from the same sources and that are trained torespond differently to their input patterns. Preliminary work in this direction has been already carried-outduring my PhD studies, in which I constructed a pattern recognition system and studied its performanceunder typical parameter variations observed in neuromorphic devices. This project will proceed further byidentifying the precise role of intrinsic variability in influencing the stochastic dynamics of learning andthus the network performance in classification. The proposed approach is radically different from typicalmachine learning techniques which are based on sequential operations running on conventional fast, preciseand power-hungry electronic hardware. Conversely, it exploits highly distributed and imprecise processingof unconventional electronic hardware, which is inhomogeneous but also extremely compact and low-power.Therefore, it offers a novel, brain-inspired strategy for enabling the construction of low-power and efficientneuromorphic devices as a valid substrate for artificial intelligence and machine learning. Because of itssimplicity, the model used for the proposed study is very general and has potential link with relevantissues in neuroscience as well, such as probabilistic computation and sensory processing in the brain.The fellowship will be based in Columbia University (New York City, NY) and thus will take advantagefrom the collaboration with world experts in theoretical neuroscience and synaptic plasticity in particularas well as engineers from industry leaders that are currently exploring neuromorphic technologies andthat are already in contact with that institution. This fellowship fits very well with my competencesin theoretical neuroscience and my interests in neuromorphic engineering and thus represents a greatopportunity for improving my academic profile.